Click here to go to a list of abstracts for these articles.

• Kimiko Aoyama, Hisaaki Kunitomo, Katsumi Tsuneno, Hisako Sato, Kazutaka Mori, and Hiroo Masuda, "Rigorous Statistical Process Variation Analysis for Quarter-Micron CMOS with Advanced TCAD Metrology", 1997 2nd International Workshop on Statistical Metrology, pp. 8-11.
• Dirk J. Bartelink, "Statistical Metrology: At the Root of Manufacturing Control", Journal of Vacuum Science Technology--Part B, Vol. 12, Issue 4, July/August 1994, pp. 2785-2794.
• Duane Boning, James Chung, Dennis Ouma, and Rajesh Divecha, "Spatial Variation in Semiconductor Processes: Modeling for Control", Electrochemical Society Proceedings, Vol. 97-9, pp. 72-83.
• E. Chang, B. Stine, T. Maung, R. Divecha, D. Bonig, J. Chung, K. Chang, G. Ray, D. Bradbury, O.S. Nakagawa, S. Oh, and D. Bartelink, "Using Statistical Metrology Framework to Identify Systematic and Random Sources of Die- and Wafer-level ILD Thickness Variation in CMP Processes", 1995 International Electron Devices Meeting, pp. 499-502.
• Sean P. Cunningham and Scott MacKinnon, "Statistical Methods for Visual Defect Metrology", IEEE Transactions on Semiconductor Manufacturing, Vol. 11, No. 1, February 1998, pp. 48-53.
• Laszlo Gutai, "Statistical Modeling of Transmission Line Model Test Structures--Part I: The Effect of Inhomogeneities on the Extracted Contact Parameters", IEEE Transactions on Electron Devices, Vol. 37, No. 11, November 1990, pp. 2350-2360.
• Itaru Kamohara, "Statistical Simulation Methodology for Multi-level Interconnect Contact Analysis and Step Coverage Evaluation", 1997 2nd International Workshop on Statistical Metrology, pp. 113-116.
• Xinhui Niu and Costas Spanos, "Statistical Enhancement of a Reflectometry Metrology System" 1997 2nd International Workshop on Statistical Metrology, pp. 40-43.
• Raman K. Nurani and J. George Shanthikumar, "The Impact of Lot-to-Lot and Wafer-to-Wafer Variations on SPC", 1997 2nd International Workshop on Statistical Metrology, pp. 110-112.
• Brian E. Stine, Duane S. Boning, and James E. Chung, "Analysis and Decomposition of Spatial Variation in Integrated Circuit Processes and Devices", IEEE Transactions on Semiconductor Manufacturing, Vol. 10, No. 1, February 1997, pp. 24-41.
• Brian E. Stine, Duane S. Boning, James E. Chung, Dennis Ciplickas, and John K. Kibarian, "Simulating the Impact of Poly-CD Wafer-Level and Die-Level Variation of Circuit Performance", 1997 2nd International Workshop on Statistical Metrology, pp. 24-27.
• Allan Y. Wong, "A Systematic Approach to Identify Critical Yield Sensitive Parametric Parameters", 1997 2nd International Workshop on Statistical Metrology, pp. 56-61.
• T. Yasuda, H. Kawashima, S. Hori, Y. Maruyama, M. Tanizawa, M. Yamawaki, and S. Asai, "A Determination Method of Worst Case MOSFET Model Parameter Using Multivariate Analysis", 1997 2nd International Workshop on Statistical Metrology, pp. 12-15.
• Crid Yu, Hua-Yu Liu, and Costas J. Spanos, "Manufacturability Evaluation of Deep Submicron Exposure Tools Using Statistical Metrology", 1995 International Symposium on Semiconductor Manufacturing, pp. 222-225.

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