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Fundamental to successful manufacturing of integrated circuits is the achievement of sufficient control in all process steps to realize, with very high yield, fully functional circuits whose performance and reliability conform to pre-determined standards. Towards this end, it is increasingly necessary to relate in a quantitative manner the sensitivity of the electrical performance of the final devices and circuits to variations in structural parameters and doping profiles, which in turn can be related to process and tool performance variations. In this paper, we describe the results of an analysis performed to quantify the sensitivity of the electrical parameters of a 0.35 micrometer LDD MOSFET to variations in the doping and structural parameters of the device that are anticipated in manufacturing. A central-composite design was used to develop second-order models for six key device electrical parameters. The resulting models are manifested as second-order equations relating the device electrical parameters variations to random variations in seven key device structure and doping parameters. This set of equations thus allows one to understand quantitatively the source and nature of the device electrical parameter variations. A simple Monte Carlo approach is applied to predict the statistical distributions of the key device electrical parameters which result from the random manufacturing variations in the structure and doping parameters by using the quantitative relationships developed in this paper.
As future technology generations for integrated circuits continue to "shrink," TCAD tools must be made more central to manufacturing issues; thus, yield optimization and design for manufacturing (DFM) should be addressed integrally with performance and reliability when using TCAD during the initial product design. This paper defines the goals for DFM in TCAD simulations and outlines a formal procedure for achieving an optimized result (ODFM). New design of experiments (DOE), weighted least squares modeling and multiple-objective mean-variance optimization methods are developed as significant parts of the new ODFM procedure. Examples of designing a 0.18-um MOSFET device are given to show the impact of device design procedures of device performance distributions and sensitivity variance profiles.
We present a novel design for manufacturing (DFM) methodology that has been applied to the design of a pass transistor for 256 Mbit DRAM. The design inputs that include gate oxide thickness, which limits the booted wordline voltage, the threshold voltage adjust implant, and the substrate bias voltage, for different channel lengths, are optimized to meet the constraints on performance, reliability, and robustness against manufacturing variations. The problems associated with applying conventional DFM techniques are discussed and a new methodology based on "margins" is presented. The results pertaining to the optimized DRAM pass transistor design for a power supply voltage Vcc = 2.5 V are presented.
The methodology, implementation, and results of a design for manufacturing (DFM) technique as applied to an integrated circuit boron base formation for an NPN transistor are presented. The primary purpose of the DFM technique is to achieve acceptable statistical prediction of the results by using the minimum number of variables and reducing the time required to perform physically-based simulations. Excellent statistical results are achieved while the number of simulations is reduced by at least a factor of five if judicious statistical techniques are applied.
In the manufacturing of VLSI circuits, process induced variations of device characteristics can drastically reduce the performance of the fabricated chips. Therefore, being able to optimize the process conditions so that device sensitivities are minimized is very important. We have developed a new response surface design methodology based on process and device simulations to estimate device variations due to changes in process input parameters around their designed values. We have made provisions in our design to make direct estimation of the gradient of the simulated device characteristics. The gradient information is used to compute device sensitivities.
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